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CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1 MANUAL CONTENTS................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-3
1.3 SPECIAL TERMINOLOGY............................................................................................ 1-4
1.4 RELATED DOCUMENTS .............................................................................................. 1-5
1.5 ELECTRONIC SUPPORT SYSTEMS........................................................................... 1-6
1.5.1 FaxBack Service .......................................................................................................1-6
1.5.2 Bulletin Board System (BBS) ....................................................................................1-7
1.5.3 CompuServe Forums ................................................................................................1-7
1.5.4 World Wide Web .......................................................................................................1-7
1.6 TECHNICAL SUPPORT ................................................................................................ 1-7
1.7 PRODUCT LITERATURE.............................................................................................. 1-8
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 Intel386 EX EMBEDDED PROCESSOR CORE............................................................ 2-1
2.2 INTEGRATED PERIPHERALS...................................................................................... 2-3
CHAPTER 3
CORE OVERVIEW
3.1 Intel386 CX PROCESSOR ENHANCEMENTS............................................................. 3-1
3.1.1 System Management Mode ......................................................................................3-1
3.1.2 Additional Address Lines ..........................................................................................3-1
3.2 Intel386 CX PROCESSOR INTERNAL ARCHITECTURE............................................ 3-2
3.2.1 Core Bus Unit ............................................................................................................3-4
3.2.2 Instruction Prefetch Unit ............................................................................................3-4
3.2.3 Instruction Decode Unit .............................................................................................3-4
3.2.4 Execution Unit ...........................................................................................................3-5
3.2.5 Segmentation Unit ....................................................................................................3-5
3.2.6 Paging Unit ...............................................................................................................3-5
3.3 CORE Intel386 EX PROCESSOR INTERFACE............................................................ 3-6
CHAPTER 4
SYSTEM REGISTER ORGANIZATION
4.1 OVERVIEW ................................................................................................................... 4-1
4.1.1 Intel386 Processor Core Architecture Registers .......................................................4-2
4.1.2 Intel386 EX Processor Peripheral Registers .............................................................4-2
4.2 I/O ADDRESS SPACE FOR PC/AT SYSTEMS ............................................................ 4-2
4.3 EXPANDED I/O ADDRESS SPACE.............................................................................. 4-3
4.4 ORGANIZATION OF PERIPHERAL REGISTERS........................................................ 4-5
4.5 I/O ADDRESS DECODING TECHNIQUES................................................................... 4-6
4.5.1 Address Configuration Register ................................................................................4-6