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12-7
DMA CONTROLLER
DMACFG register), but the Requester address registers would be programmed with one of the
memory addresses. It doesn’t really matter which memory is the Requester and which is the Tar-
get, as long as the transfer direction is set to provide the correct Source and Destination.
12.2.2.4 Ready Generation For DMA Cycles
DMA cycles are identical to any other type of memory or I/O cycles in terms of how they are
completed. A valid READY# must be sampled at the end of the last T2 state in order to complete
a DMA Read or Write cycle. This READY# may be generated externally, or internally using the
appropriate chip select unit (see Chapter 14, “CHIP-SELECT UNIT” for a description of gener-
ating READY# internally).
12.2.2.5 DMA Usage of the 4-Byte Temporary Register
Each DMA channel has a 4-byte temporary FIFO register used for temporary data storage during
two cycle transfers. The way the DMA channel fills and empties this register depends on the data
transfer mode, the bus sizes of the source and destination, and the data transfer direction. The fol-
lowing describes how the Temporary Register is filled and emptied for the Read and Write Trans-
fer Directions.
Filling the Temporary Register:
Read Cycle In a Read Cycle data is transferred from the Requester to the Target. Each request
(DREQn) in a Read Cycle results in the DMA transferring a byte (if requester is
an 8-bit device) or a word (if the requester is a 16-bit device) from the Source
(Requester) to the temporary register. This continues until either the Temporary
Register is full, or until the byte count or terminal count is reached.
Write Cycle In a Write Cycle data is transferred from the Target to the Requester. The first
request (DREQn) initiates a fill of the temporary register (four byte reads of the
Target if the Target is 8-bit, or two word reads if it is 16-bit). The buffer is
considered full if either four bytes have been stored, or if less than four bytes, the
byte count or terminal count has been reached.
Emptying the Temporary Register:
Read Cycle Once the Temporary Register has been filled the DMA empties it by doing four
byte write cycles (if Target is 8-bit), or two word write cycles (if Target is 16-bit).
This is done in a burst-type fashion since all four requests have already occurred.
The byte counter is decremented after each write has occurred.
Write Cycle Once the Temporary Register has been filled the DMA does a single write cycle
transferring the first byte (if Requester is 8-bit), or the first word (if Requester is
16-bit). This first write cycle happens immediately after the buffer has been
filled. Each subsequent request (DREQn) results in another write cycle
transferring another byte or word from the Temporary Register to the Requester.
This continues until either the Temporary Register is empty, or byte count or
terminal count has been reached.