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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
8-10
8.3.2 Powerdown Mode
Powerdown mode freezes both the core clocks and the peripheral clocks (PH1C and PH1P low,
PH2C and PH2P high). The BIU cannot acknowledge DMA, refresh, and external hold requests
in powerdown mode, since all the clocks are frozen.
To enter powerdown mode, follow these steps:
1. Program the PWRCON register (Figure 8-5).
2. Execute a HALT instruction.
3. The CPU enters powerdown mode when READY# (internal or external) terminates the
halt bus cycle.
When P3.6/PWRDOWN is configured as a peripheral pin, the pin goes high when the clocks stop,
to indicate that the device is in powerdown mode. (Chapter 16 explains how to configure the pin
as either a peripheral pin or a general-purpose I/O port pin.)
8.3.3 Ready Generation During HALT
A halt cycle, like all other CPU bus cycles, requires a valid READY# to complete. This ready can
be generated by either external logic, or from the internal bus interface unit (BIU). Setting bit 2
of the PWRCON causes the READY# to be generated by the internal BIU, and clearing bit 2
requires it to be generated by external logic. When READY# is generated internally the LBA#
signal is driven low.
External logic can use the PWRDOWN output to control other system components and prevent
DMA and hold requests.
NOTE
When the processor exits Powerdown Mode, use the CLKOUT pin for
external synchronization with the processor clock.