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E-1
APPENDIX E
INSTRUCTION SET SUMMARY
This appendix provides reference information for the Intel386™ processor family instruction set.
The appendix is organized as follows:
• Instruction Encoding and Clock Count Summary (see below)
• Instruction Encoding (page E-22)
E.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY
To calculate elapsed time for an instruction, multiply the instruction clock count, as listed in Table
E-1, by the processor clock period (e.g., 62.5 ns for 16 MHz).
Instruction clock count assumptions:
• The instruction has been prefetched, decoded, and is ready for execution.
• Bus cycles do not require wait states.
• There are no local bus HOLD requests delaying processor access to the bus.
• No exceptions are detected during instruction execution.
• When an effective address is calculated, it does not use two general register components.
One register, scaling and displacement can be used within the clock counts shown.
However, when the effective address calculation uses two general register components, add
1 clock to the clock count shown.
Instruction clock count notation:
• When two clock counts are given, the smaller refers to a register operand and the larger
refers to a memory operand.
• n = number of times repeated.
• m = number of components in the next instruction executed, where the entire displacement
(if any) counts as one component, the entire immediate data (if any) counts as one
component, and all other bytes of the instruction and prefix(es) of each count as one
component.
Misaligned or 32-bit operand accesses:
• When instructions access a misaligned 16-bit operand or 32-bit operand on even address:
— add 2* clocks for read or write
— add 4** clocks for read and write
• When instructions access a 32-bit operand on odd address:
— add 4* clocks for read or write
— add 8** clocks for read and write