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Intel386™ EX MICROPROCESSOR USER’S MANUAL
xii
CHAPTER 18
JTAG TEST-LOGIC UNIT
18.1 OVERVIEW ................................................................................................................. 18-1
18.2 TEST-LOGIC UNIT OPERATION................................................................................ 18-3
18.2.1 Test Access Port (TAP) ..........................................................................................18-3
18.2.2 Test Access Port (TAP) Controller ..........................................................................18-4
18.2.3 Instruction Register (IR) ..........................................................................................18-7
18.2.4 Data Registers ........................................................................................................18-8
18.3 TESTING................................................................................................................... 18-10
18.3.1 Identifying the Device ............................................................................................18-10
18.3.2 Bypassing Devices on a Board .............................................................................18-10
18.3.3 Sampling Device Operation and Preloading Data .................................................18-10
18.3.4 Testing the Interconnections (EXTEST) ................................................................18-10
18.3.5 Disabling the Output Drivers .................................................................................18-11
18.4 TIMING INFORMATION............................................................................................ 18-12
18.5 DESIGN CONSIDERATIONS.................................................................................... 18-14
APPENDIX A
SIGNAL DESCRIPTIONS
APPENDIX B
COMPATIBILITY WITH THE PC/AT* ARCHITECTURE
B.1 HARDWARE DEPARTURES FROM PC/AT SYSTEM ARCHITECTURE................... B-1
B.1.1 DMA Unit ................................................................................................................ B-1
B.1.2 Industry Standard Bus (ISA) Signals ...................................................................... B-2
B.1.3 Interrupt Control Unit .............................................................................................. B-4
B.1.4 SIO Units ................................................................................................................B-4
B.1.5 CPU-only Reset ...................................................................................................... B-4
B.1.6 HOLD, HLDA Pins .................................................................................................. B-4
B.1.7 Port B ......................................................................................................................B-5
B.2 SOFTWARE CONSIDERATIONS FOR A PC/AT SYSTEM ARCHITECTURE............ B-5
B.2.1 Embedded Basic Input Output System (BIOS) ....................................................... B-5
B.2.2 Embedded Disk Operating System (DOS) ..............................................................B-5
B.2.3 Microsoft* Windows* ............................................................................................... B-5
APPENDIX C
EXAMPLE CODE HEADER FILES
C.1 REGISTER DEFINITIONS FOR CODE EXAMPLES ................................................... C-1
C.2 EXAMPLE CODE DEFINES......................................................................................... C-6