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Intel386™ EX MICROPROCESSOR USER’S MANUAL
xxii
TABLES
Table Page
2-1 PC-compatible Peripherals...........................................................................................2-3
2-2 Embedded Application-specific Peripherals.................................................................2-4
4-1 Peripheral Register I/O Address Map in Slot 15...........................................................4-5
4-2 Peripheral Register Addresses...................................................................................4-15
5-1 Master’s IR3 Connections ............................................................................................5-8
5-2 Master’s IR4 Connections ............................................................................................5-8
5-3 Signal Pairs on Pins without a Multiplexer..................................................................5-23
5-4 Example Pin Configuration Registers.........................................................................5-30
5-5 Example DMACFG Configuration Register................................................................5-31
5-6 Example TMRCFG Configuration Register ................................................................5-32
5-7 Example INTCFG Configuration Register ..................................................................5-33
5-8 Example SIOCFG Configuration Register..................................................................5-33
5-9 Pin Configuration Register Design Woksheet ............................................................5-34
5-10 DMACFG Register Design Worksheet.......................................................................5-35
5-11 TMRCFG Register Design Worksheet .......................................................................5-36
5-12 INTCFG Register Design Worksheet .........................................................................5-37
5-13 SIOCFG Register Design Worksheet.........................................................................5-37
6-1 Bus Interface Unit Signals............................................................................................6-3
6-2 Bus Status Definitions ..................................................................................................6-5
6-3 Sequence of Nonaligned Bus Transfers.....................................................................6-10
7-1 CR0 Bits Cleared Upon Entering SMM ........................................................................7-3
7-2 SMM Processor State Initialization Values...................................................................7-4
7-3 Relative Priority of Exceptions and Interrupts...............................................................7-7
8-1 Clock and Power Management Registers....................................................................8-6
8-2 Clock and Power Management Signals........................................................................8-6
9-1 82C59A Master and Slave Interrupt Sources...............................................................9-5
9-2 ICU Registers.............................................................................................................9-16
10-1 TCU Signals ...............................................................................................................10-3
10-2 TCU Associated Registers .........................................................................................10-4
10-3 Operations Caused by GATE
n...................................................................................10-6
10-4 GATE
n
Connection Options.....................................................................................10-20
10-5 Minimum and Maximum Initial Counts......................................................................10-26
10-6 Results of Multiple Read-back Commands Without Reads......................................10-33
11-1 SIO Signals ................................................................................................................11-3
11-2 Maximum and Minimum Output Bit Rates..................................................................11-5
11-3 Divisor Values for Common Bit Rates........................................................................11-5
11-4 Status Signal Priorities and Sources ........................................................................11-13
11-5 SIO Registers...........................................................................................................11-15
11-6 Access to Multiplexed Registers...............................................................................11-16
12-1 DMA Signals...............................................................................................................12-4
12-2 Operations Performed During Transfer......................................................................12-6
12-3 DMA Registers .........................................................................................................12-28
12-4 DMA Software Commands.......................................................................................12-50
13-1 SSIO Signals..............................................................................................................13-4