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BUS INTERFACE UNIT
Figure 6-11. Basic Refresh Cycle
A2491-02
LOCK#
D15:0
CLK2
BHE#, BLE#
M/IO#, D/C#
Valid 1
RD#
READY#
Ti T1 T2 Ti T1 T2 T2 Ti Ti T1
Cycle 1
Nonpipelined
External
(Read)
Cycle 2
Refresh
CLKOUT
Idle Idle Cycle 3
Nonpipelined
External
(Write)
[Late Ready]
T2
Valid 3
ADS#
NA#
A25:1
W/R#
WR#
LBA#
Idle
REFRESH#
Float
HOLD
HLDA
In
Out
Valid 1
Valid 2
Valid 1 Valid 2
Valid 3