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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
17-12
17.5 DESIGN CONSIDERATIONS
This section outlines design considerations for the watchdog timer unit.
Depending on the system configuration, a WDT timeout can cause a maskable interrupt, a non-
maskable interrupt, or a system reset.
Maskable interrupt The WDT timeout signal is internally inverted and connected to the
interrupt control unit’s slave IR7 line. If you want a WDT timeout to
generate a slave IR7 interrupt (maskable interrupt), you need only
enable (unmask) the interrupt (Refer to Chapter 9, for details).
Ensure that the slave 8259A is configured for edge-triggered
interrupts (refer to Chapter 9, Interrupt Control Unit) if IR7 is
unmasked. Otherwise, the WDT generates continuous interrupts.
Nonmaskable interrupt If you want a WDT timeout to cause a nonmaskable interrupt,
connect the WDTOUT pin to the NMI input pin.
Reset If you want a WDT timeout to reset the system, connect the
WDTOUT pin to the RESET input pin.
17.6 PROGRAMMING CONSIDERATIONS
This section outlines programming considerations for the watchdog timer unit.
17.6.1 Writing to the WDT Reload Registers (WDTRLDH and WDTRLDL)
WDTRLDH and WDTRLDL are 16 bit registers at addresses 0F4C0H and 0F4C2H respectively.
Therefore, when using a 32-bit write to load the two registers, the lower 16 bits should contain
the data for WDTRLDH and the higher 16 bits should contain the data for WDTRLDL.
For example, 4321H can be written to WDTRLDH and 0CCCCH to WDTRLDL using a 32-bit
write of the number 0CCCC4321H to I/O address 0F4C0H.
17.6.2 Minimum Counter Reload Value
To ensure correct operation of the Watchdog Timer, the WDT’s counter should never be reloaded
with a value less than 8.
17.6.3 Watchdog Timer Unit Code Examples
This section includes these software routines:
ReLoadDownCounter Initiates a lockout sequence
GetWDT_Count Reads the value of the counter
WDT_BusMonitor Places the WDT in Bus Monitor Mode
EnableWDTInterrupt Enables WDT interrupts