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Intel386™ EX MICROPROCESSOR USER’S MANUAL
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7.3.4.2 SMRAM State Dump Area .................................................................................7-14
7.3.5 Resume Instruction (RSM) ......................................................................................7-15
7.4 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS ....................................... 7-15
7.5 PROGRAMMING CONSIDERATIONS........................................................................ 7-16
7.5.1 System Management Mode Code Example ............................................................7-16
CHAPTER 8
CLOCK AND POWER MANAGEMENT UNIT
8.1 OVERVIEW ................................................................................................................... 8-1
8.1.1 Clock Generation Logic .............................................................................................8-1
8.1.2 Power Management Logic ........................................................................................8-3
8.1.2.1 SMM Interaction with Power Management Modes ...............................................8-4
8.1.2.2 Bus Interface Unit Operation During Idle Mode ....................................................8-5
8.1.2.3 Watchdog Timer Unit Operation During Idle Mode ..............................................8-5
8.1.3 Clock and Power Management Registers and Signals .............................................8-6
8.2 CONTROLLING THE PSCLK FREQUENCY ................................................................ 8-7
8.3 CONTROLLING POWER MANAGEMENT MODES ..................................................... 8-8
8.3.1 Idle Mode ..................................................................................................................8-9
8.3.2 Powerdown Mode ...................................................................................................8-10
8.3.3 Ready Generation During HALT .............................................................................8-10
8.4 DESIGN CONSIDERATIONS...................................................................................... 8-11
8.4.1 Reset Considerations ..............................................................................................8-11
8.4.2 Power-up Considerations ........................................................................................8-12
8.4.2.1 Built-in Self Test .................................................................................................8-12
8.4.2.2 JTAG Reset ........................................................................................................8-12
8.4.3 Powerdown Mode and Idle Mode Considerations ...................................................8-13
8.5 PROGRAMMING CONSIDERATIONS........................................................................ 8-13
8.5.1 Clock and Power Management Unit Code Example ...............................................8-13
CHAPTER 9
INTERRUPT CONTROL UNIT
9.1 OVERVIEW ................................................................................................................... 9-1
9.2 ICU OPERATION........................................................................................................... 9-4
9.2.1 Interrupt Sources ......................................................................................................9-4
9.2.2 Interrupt Priority ........................................................................................................9-6
9.2.2.1 Assigning an Interrupt Level .................................................................................9-6
9.2.2.2 Determining Priority ..............................................................................................9-7
9.2.3 Interrupt Vectors .......................................................................................................9-8
9.2.4 Interrupt Process .......................................................................................................9-9
9.2.5 Poll Mode ................................................................................................................9-14
9.3 REGISTER DEFINITIONS........................................................................................... 9-15
9.3.1 Port 3 Configuration Register (P3CFG) ..................................................................9-18
9.3.2 Interrupt Configuration Register (INTCFG) .............................................................9-19