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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-14
3. When a chip-select region is enabled for the current read cycle but internal READY#
generation is disabled for that region, and the Chip-select Unit is programmed to insert
wait-states, the READY# signal is ignored (not sampled) by the processor until the
programmed number of wait-states are inserted into the cycle.
4. At the falling edge of PH2 in every T2 state (after the wait-states, if any are programmed
in the Chip-select Unit, have expired), READY# is sampled. If READY# is active, the
processor reads the input data on the data bus and deactivates RD#.
5. If READY# is high, wait states are added (additional T2 states for nonpipelined cycles)
until READY# is sampled low. READY# is sampled at the end of each T2 state (at the
falling edge of PH2).
6. Once READY# is sampled low, the processor reads the input data, deactivates RD#, and
terminates the read cycle. If a new bus cycle is pending, it begins on the next T-state.