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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-24
NOTE
Since the CAS lines are invalid in the Ti states between the two interrupt
acknowledge cycles, cascading of external 82C59A devices requires latching
the CAS lines. This ensures that the CAS lines remain valid during these Ti
states to fulfill the requirements of the external 82C59A devices.
2. The processor floats D15:0 for both cycles; however, at the end of the second cycle, if the
interrupt is from an external cascaded 82C59A, the service-routine vector number driven
on the lower data bus by the 82C59A is read by the processor on data pins D7:0.
Otherwise, the active internal 82C59A sends the vector to the processor.
3. The first cycle is always an internal cycle and the second may be internal or external.
Therefore, READY# is generated internally for the first cycle and for the second cycle, if
the interrupt request is from one of the internal 82C59A modules. If the interrupt is from a
cascaded external 82C59A, external logic must assert READY# to terminate the second
cycle. The internal Chip-select Unit can not generate READY# for the second interrupt
acknowledge cycle.