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4-18 PPC405 Core User’s Manual
4.6.4 Sequential Cache Operations
Some common cache operations, when performed sequentially, can limit DCU performance:
sequential loads/stores to non-cachable storage regions, sequential line fills, and sequential line
flushes.
In the case of sequential cache hits, the most commonly occurring operations, the DCU loads or
stores data every cycle. In such cases, the DCU does not limit performance.
However, when a load from a non-cachable storage region is followed by multiple loads from non-
cachable regions, the loads can complete no faster than every four cycles, assuming that the
addresses are accepted during the same cycle in which it is requested, and that the data is returned
during the cycle after the load is accepted.
Similarly, when a store to a non-cachable storage region is followed by multiple stores to non-
cachable regions the fastest that the stores can complete is every other cycle. The DCU can have
accepted up to three stores before additional DCU commands will stall waiting for the prior stores to
complete.
Sequential line fills can limit DCU performance. Line fills occur when a load/store or dcbt instruction
misses in the cache, and can be pipelined on the PLB interface such that up to two requests can be
accepted before stalling subsequent requests. The subsequent operations will wait in the DCU until
the first line fill completes. The line fills must complete in the order that they are accepted.
Sequential line flushes from the DCU to main memory also limit DCU performance. Flushes occur
when a line fill replaces a valid line that is marked dirty (modified), or when a dcbf instruction flushes
a specific line. If two flushes are pending, the DCU stalls any new data cache operations until the first
flush finishes and the second flush begins.