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2-20 PPC405 Core User’s Manual
When address translation is enabled (MSR[IR] = 1 or MSR[DR] = 1), the E field in the corresponding
TLB entry controls the endianness of a memory region. When address translation is disabled
(MSR[IR] = 0 or MSR[DR] = 0), the SLER controls the endianness of a memory region.
Bytes in storage that are accessed as little endian are arranged in true little endian format. The
PPC405 does not support the little endian mode defined in the PowerPC architecture and used in
PPC401xx and PPC403xx processors. Furthermore, no address modification is performed when
accessing storage regions programmed as little endian. Instead, the PPC405 reorders the bytes as
they are transferred between the processor and memory.
The on-the-fly reversal of bytes in little endian storage regions is handled in one of two ways,
depending on whether the storage access is an instruction fetch or a data access (load/store). The
following sections describe byte reordering for the two kinds of storage accesses.
2.5.3.1 Fetching Instructions from Little Endian Storage Regions
Instructions are words (four bytes) that are aligned on word boundaries in memory. As such,
instructions in a big endian memory region are arranged with the most significant byte (MSB) of the
instruction word at the lowest address.
Consider the big endian mapping of instruction
p
at address 00, where, for example,
p
= add r7, r7, r4:
On the other hand, in the little endian mapping instruction
p
is arranged with the least significant byte
(LSB) of the instruction word at the lowest numbered address:
When an instruction is fetched from memory, the instruction must be placed in the instruction queue in
the proper order. The execution unit assumes that the MSB of an instruction word is at the lowest
address. Therefore, when instructions are fetched from little endian storage regions, the four bytes of
an instruction word are reversed before the instruction is decoded. In the PPC405 core, the byte
reversal occurs between memory and the instruction cache unit (ICU). The ICU always stores
instructions in big endian format, regardless of whether the memory region containing the instruction
is programmed as big endian or little endian. Thus, the bytes are already in the proper order when an
instruction is transferred from the ICU to the decode stage of the pipeline.
If a storage region is reprogrammed from one endian format to the other, the storage region must be
reloaded with program and data structures in the appropriate endian format. If the endian format of
instruction memory changes, the ICU must be made coherent with the updates. The ICU must be
invalidated and the updated instruction memory using the new endian format must be fetched so that
the proper byte ordering occurs before the new instructions are placed in the ICU.
MSB LSB
0x00 0x01 0x02 0x03
LSB MSB
0x00 0x01 0x02 0x03