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7-6 PPC405 Core User’s Manual
M (memory coherent,1 bit)
For implementations that support multiprocessing, the M storage attribute improves the performance
of memory coherency management. Because the PPC405 does not provide multi-processor support
or hardware support for data coherency, the M bit is implemented, but has no effect.
G (guarded,1 bit)
When set (TLBLO_entry[G] = 1), indicates that the hardware cannot speculatively access the location
for pre-fetching or out-of-order load access. The G storage attribute is typically used to protect
memory-mapped I/O from inadvertent access. Attempted execution of an instruction from a guarded
data storage address while instruction address translation is enabled results in an instruction storage
interrupt because data storage and memory mapped I/O (MMIO) addresses are not used to contain
instructions.
An instruction fetch from a guarded region does not occur until the execution pipeline is empty, thus
guaranteeing that the access is necessary and therefore not speculative. For this reason,
performance is degraded when executing out of guarded regions, and software should avoid
unnecessarily marking regions of instruction storage as guarded.
In real mode, the Storage Guarded Register (SGR) controls guarding.
U0 (user-defined attribute, 1 bit)
When set (TLBLO[U0] = 1), indicates the user-defined attribute applies to the data in the associated
page.
In real mode, the Storage User-defined 0 Register (SU0R) controls the setting of the U0 storage
attribute.
E (endian, 1 bit)
When set (TLBLO[E] = 1), indicates that data in the associated page is stored in true little endian
format.
In real mode, the Storage Little-Endian Register (SLER) controls the setting of the E storage attribute.
7.3.3 Shadow Instruction TLB
To enhance performance, four instruction-side TLB entries are kept in a four-entry fully-associative
shadow array. This array, called the instruction TLB (ITLB), helps to avoid TLB contention between
instruction accesses to the TLB and load/store operations. Replacement and invalidation of the ITLB
entries is managed by hardware. See “Shadow TLB Consistency” on page 7-7 for details.
The ITLB can be considered a level-1 instruction-side TLB; the UTLB serves as the level-2
instruction-side TLB. The ITLB is used only during instruction fetches for storing instruction address
translations. Each ITLB entry contains the translation information for a page. The processor uses the
ITLB for address translation of instruction accesses when MSR[IR] = 1.