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SRR0
Save/Restore Register 0
10-42 PPC405 Core User’s Manual
SRR0
SPR 0x01A
See “Save/Restore Registers 0 and 1 (SRR0–SRR1)” on page 5-9.
.
Figure 10-26. Save/Restore Register 0 (SRR0)
0:29 SRR0 receives an instruction address when a non-critical interrupt is taken;
the Program Counter is restored from SRR0 when rfi executes.
30:31
Reserved
0 29 30 31