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Programming Model 2-31
which certain instructions cannot be executed, is called the “user mode,” or “problem state.” These
terms are used in pairs:
The architecture uses MSR[PR] to control the execution mode. When MSR[PR] = 1, the processor is
in user mode (problem state); when MSR[PR] = 0, the processor is in privileged mode (supervisor
state).
After a reset, MSR[PR] = 0.
2.9.1 MSR Bits and Exception Handling
The current value of MSR[PR] is saved, along with all other MSR bits, in the SRR1 (for non-critical
interrupts) or SRR3 (for critical interrupts) upon any interrupt, and MSR[PR] is set to 0. Therefore, all
exception handlers operate in privileged mode.
Attempting to execute a privileged instruction while in user mode causes a privileged violation
program exception (see “Program Interrupt” on page 5-20). The PPC405 core does not execute the
instruction, and the program counter is loaded with EVPR[0:15] || 0x0700, the address of an
exception processing routine.
The PRR field of the Exception Syndrome Register (ESR) is set when an interrupt was caused by a
privileged instruction program exception. Software is not required to clear ESR[PPR].
2.9.2 Privileged Instructions
The instructions listed in Table 2-9 are privileged and cannot be executed while in user mode
(MSR[PR] = 1).
Privileged Non-privileged
Privileged Mode User Mode
Supervisor State Problem State
Table 2-9. Privileged Instructions
dcbi
dccci
dcread
iccci
icread
mfdcr
mfmsr
mfspr
For all SPRs except CTR, LR, SPRG4–SPRG7, and XER. See
“Privileged SPRs” on page 2-32
mtdcr
mtmsr
mtspr
For all SPRs except CTR, LR, XER. See “Privileged SPRs” on page 2-32
rfci
rfi