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Instruction Set 9-47
dcba
Data Cache Block Allocate
dcba
Data Cache Block Allocate
EA ← (RA|0) + (RB)
DCBA(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents
of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is in the data cache and the EA is marked as cachable and non-write-
through, the data in the cache block is architecturally undefined. For the PPC405 core, the cache data
block is set to 0.
If the data block at the EA is not in the data cache and the EA is marked as cachable and not marked
as write-through, a cache block is established and set to an architecturally-undefined value. Note that
no data is read from main storage, as described in the programming note.
If the data block at the EA is marked as non-cachable, a no-op occurs.
If the data block at the EA is in the data cache and marked as write-through, architecturally the data in
the cache block can be left unmodified. Alternatively, the data block at the EA can be undefined in the
data cache and in main storage. For the PPC405 core, a no-op occurs.
If the data block at the EA is not in the data cache and marked as write-through, architecturally the
instruction can establish a cache block and set the block to 0, or a no-op can occur. For the PPC405
core, a no-op occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
Because dcba can establish an address in the data cache without copying the contents of that
address from main storage, the address established can be invalid with respect to main storage. A
subsequent operation may cause the address to be copied back to main storage, for example, to
make room for a new cache block; a machine check exception could occur under these
circumstances.
dcba provides a hint that a block of storage will soon be stored to or no longer needed; there is no
need to retain the data in the block. Establishing the line in the cache, without reading from main
storage, improves performance.
dcba RA, RB
31 RA RB 758
0 6 11 16 21 31