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TCR
Timer Control Register
10-50 PPC405 Core User’s Manual
TCR
SPR 0x3DA
See “Timer Control Register (TCR)” on page 6-9.
Figure 10-33. Timer Control Register (TCR)
0:1 WP Watchdog Period
00 2
17
clocks
01 2
21
clocks
10 2
25
clocks
11 2
29
clocks
2:3 WRC Watchdog Reset Control
00 No Watchdog reset will occur.
01 Core reset will be forced by the
Watchdog.
10 Chip reset will be forced by the
Watchdog.
11 System reset will be forced by the
Watchdog.
TCR[WRC] resets to 00.
This field can be set by software, but
cannot be cleared by software, except by a
software-induced reset.
4 WIE Watchdog Interrupt Enable
0 Disable watchdog interrupt.
1 Enable watchdog interrupt.
5 PIE PIT Interrupt Enable
0 Disable PIT interrupt.
1 Enable PIT interrupt.
6:7 FP FIT Period
00 2
9
clocks
01 2
13
clocks
10 2
17
clocks
11 2
21
clocks
8 FIE FIT Interrupt Enable
0 Disable FIT interrupt.
1 Enable FIT interrupt.
9 ARE Auto Reload Enable
0 Disable auto reload.
1 Enable auto reload.
Disables on reset.
10:31
Reserved
012345678910 31
WP
WRC
WIE
PIE
FP FIE
ARE