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Overview 1-7
The time base is a 64-bit counter incremented either by an internal signal equal to the CPU clock rate
or by a separate external timer clock signal. No interrupts are generated when the time base rolls
over.
The PIT is a 32-bit register that is decremented at the same rate as the time base is incremented. The
user loads the PIT register with a value to create the desired delay. When a decrement occurs on a
PIT count of 1, the timer stops decrementing, a bit is set in the Timer Status Register (TSR), and a
PIT interrupt is generated. Optionally, the PIT can be programmed to reload automatically the last
value written to the PIT register, after which the PIT begins decrementing again.The Timer Control
Register (TCR) contains the interrupt enable for the PIT interrupt.
The FIT generates periodic interrupts based on selected bits in the time base. Users can select one of
four intervals for the timer period by setting the appropriate bits in the TCR. When the selected bit in
the time base changes from 0 to 1, a bit is set in the TSR and a FIT interrupt is generated. The FIT
interrupt enable is contained in the TCR.
The watchdog timer generates a periodic interrupt based on selected bits in the time base. Users can
select one of four time periods for the interval and the type of reset generated if the watchdog timer
expires twice without an intervening clear from software.
1.4.4 Debug
The processor core debug facilities include debug modes for the various types of debugging used
during hardware and software development. Also included are debug events that allow developers to
control the debug process. Debug modes and debug events are controlled using debug registers in
the chip. The debug registers are accessed either through software running on the processor, or
through the JTAG port. The JTAG port can also be used for board test.
The debug modes, events, controls, and interfaces provide a powerful combination of debug facilities
for hardware and software development tools.
1.4.4.1 Development Tool Support
The PPC405 supports a wide range of hardware and software development tools.
An operating system debugger is an example of an operating system-aware debugger, implemented
using software traps.
RISCWatch is an example of a development tool that uses the external debug mode, debug events,
and the JTAG port to support hardware and software development and debugging.
The RISCTrace™ feature of RISCWatch is an example of a development tool that uses the real-time
trace capability of the processor core.
1.4.4.2 Debug Modes
The internal, external,real-time-trace, and debug wait modes support a variety of debug tool used in
embedded systems development. These debug modes are described in detail in “Debug Modes” on
page 8-1.
1.4.5 Core Interfaces
The core provides a range of I/O interfaces that simplify the attachment of on-chip and off-chip
devices.