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CCR0
Core Configuration Register 0
10-6 PPC405 Core User’s Manual
CCR0
SPR 0x3B3
See “Core Configuration Register 0 (CCR0)” on page 4-11.
Figure 10-1. Core Configuration Register 0 (CCR0)
0:5 Reserved
6 LWL Load Word as Line
0 The DCU performs load misses or non-
cachable loads as words, halfwords, or
bytes, as requested
1 For load misses or non-cachable loads,
the DCU moves eight words (including
the target word) into the line fill buffer
7 LWOA Load Without Allocate
0 Load misses result in line fills
1 Load misses do not result in a line fill, but
in non-cachable loads
8 SWOA Store Without Allocate
0 Store misses result in line fills
1 Store misses do not result in line fills, but
in non-cachable stores
9 DPP1 DCU PLB Priority Bit 1
0 DCU PLB priority 0 on bit 1
1 DCU PLB priority 1 on bit 1
Note:DCU logic dynamically controls DCU
priority bit 0.
10:11 IPP ICU PLB Priority Bits 0:1
00 Lowest ICU PLB priority
01 Next to lowest ICU PLB priority
10 Next to highest ICU PLB priority
11 Highest ICU PLB priority
12:13
Reserved
14 U0XE Enable U0 Exception
0 Disables the U0 exception
1 Enables the U0 exception
15 LDBE Load Debug Enable
0 Load data is invisible on data-side (on-
chip memory (OCM)
1 Load data is visible on data-side OCM
16:19
Reserved
20 PFC ICU Prefetching for Cachable Regions
0 Disables prefetching for cachable
regions
1 Enables prefetching for cachable regions
0 56789101112 13 14 15 16 19 20 21 22 23 24 26 27 28 30 31
CWS
CIS
LWL
LWOA
SWOA
U0XE
LBDE
PFC
PFNC FWOA
NCRSDPP1
IPP