Filter
Top Products
Contents v
Contents
Figures ......................................................................................................................................xv
Tables .....................................................................................................................................xviii
About This Book .....................................................................................................................xxi
Who Should Use This Book .............................................................................................................................. xxi
How to Use This Book ...................................................................................................................................... xxi
Conventions ..................................................................................................................................................... xxii
Chapter 1. Overview ...............................................................................................................1-1
PPC405 Features ............................................................................................................................................ 1-1
PowerPC Architecture ...................................................................................................................................... 1-3
The PPC405 as a PowerPC Implementation ................................................................................................... 1-3
Processor Core Organization ........................................................................................................................... 1-4
Instruction and Data Cache Controllers ...................................................................................................... 1-4
Instruction Cache Unit ............................................................................................................................ 1-4
Data Cache Unit ..................................................................................................................................... 1-5
Memory Management Unit .......................................................................................................................... 1-5
Timer Facilities ............................................................................................................................................ 1-6
Debug .......................................................................................................................................................... 1-7
Development Tool Support ..................................................................................................................... 1-7
Debug Modes ......................................................................................................................................... 1-7
Core Interfaces ............................................................................................................................................ 1-7
Processor Local Bus ............................................................................................................................... 1-8
Device Control Register Bus ................................................................................................................... 1-8
Clock and Power Management ............................................................................................................... 1-8
JTAG ....................................................................................................................................................... 1-8
Interrupts ................................................................................................................................................ 1-8
Auxiliary Processor Unit .......................................................................................................................... 1-8
On-Chip Memory .................................................................................................................................... 1-8
Data Types .................................................................................................................................................. 1-8
Processor Core Register Set Summary ...................................................................................................... 1-9
General Purpose Registers .................................................................................................................... 1-9
Special Purpose Registers ..................................................................................................................... 1-9
Machine State Register .......................................................................................................................... 1-9
Condition Register .................................................................................................................................. 1-9
Device Control Registers ........................................................................................................................ 1-9
Addressing Modes ..................................................................................................................................... 1-10
Chapter 2. Programming Model ............................................................................................2-1
User and Privileged Programming Models ...................................................................................................... 2-1
Memory Organization and Addressing ............................................................................................................. 2-1
Storage Attributes ........................................................................................................................................ 2-2
Registers .......................................................................................................................................................... 2-2
General Purpose Registers (R0-R31) ......................................................................................................... 2-5
Special Purpose Registers .......................................................................................................................... 2-5
Count Register (CTR) ............................................................................................................................. 2-6
Link Register (LR) .................................................................................................................................. 2-7
Fixed Point Exception Register (XER) .................................................................................................... 2-7
Special Purpose Register General (SPRG0–SPRG7) ............................................................................ 2-9
Processor Version Register (PVR) ....................................................................................................... 2-10
Condition Register (CR) ............................................................................................................................ 2-10
CR Fields after Compare Instructions ................................................................................................... 2-11