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9-70 PPC405 Core User’s Manual
isync
Instruction Synchronize
isync
Instruction Synchronize
The isync instruction is a context synchronizing instruction.
isync provides an ordering function for the effects of all instructions executed by the processor.
Executing isync insures that all instructions preceding the isync instruction execute before isync
completes, except that storage accesses caused by those instructions need not have completed.
No subsequent instructions are initiated by the processor until isync completes. Finally, execution of
isync causes the processor to discard any prefetched instructions, with the effect that subsequent
instructions are fetched and executed in the context established by the instructions preceding isync.
isync has no effect on caches.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Note
See the discussion of context synchronizing instructions in “Synchronization” on page 2-33.
The following code example illustrates the necessary steps for self-modifying code. This example
assumes that addr1 is both data and instruction cachable.
stw regN, addr1 # data in regN is to become an instruction at addr1
dcbst addr1 # forces data from the data cache to memory
sync # wait until the data actually reaches the memory
icbi addr1 # the previous value at addr1 might already be in
the instruction cache; invalidate in the cache
isync # the previous value at addr1 might already have been
pre-fetched into the queue; invalidate the queue
so that the instruction must be re-fetched
Architecture Note
This instruction is part of the IBM PowerPC Embedded Virtual Environment.
isync
19 150
0 6 21 31