Filter
Top Products
4-12 PPC405 Core User’s Manual
8 SWOA Store Without Allocate
0 Store misses result in line fills
1 Store misses do not result in line fills, but
in non-cachable stores
9 DPP1 DCU PLB Priority Bit 1
0 DCU PLB priority 0 on bit 1
1 DCU PLB priority 1 on bit 1
Note:DCU logic dynamically controls DCU
priority bit 0.
10:11 IPP ICU PLB Priority Bits 0:1
00 Lowest ICU PLB priority
01 Next to lowest ICU PLB priority
10 Next to highest ICU PLB priority
11 Highest ICU PLB priority
12:13
Reserved
14 U0XE Enable U0 Exception
0 Disables the U0 exception
1 Enables the U0 exception
15 LDBE Load Debug Enable
0 Load data is invisible on data-side (on-
chip memory (OCM)
1 Load data is visible on data-side OCM
16:19
Reserved
20 PFC ICU Prefetching for Cachable Regions
0 Disables prefetching for cachable
regions
1 Enables prefetching for cachable regions
21 PFNC ICU Prefetching for Non-Cachable Regions
0 Disables prefetching for non-cachable
regions
1 Enables prefetching for non-cachable
regions
22 NCRS Non-cachable ICU request size
0 Requests are for four-word lines
1 Requests are for eight-word lines
23 FWOA Fetch Without Allocate
0 An ICU miss results in a line fill.
1 An ICU miss does not cause a line fill,
but results in a non-cachable fetch.
24:26
Reserved
27 CIS Cache Information Select
0 Information is cache data.
1 Information is cache tag.
28:30
Reserved
31 CWS Cache Way Select
0 Cache way is A.
1 Cache way is B.