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B-8 PPC405 Core User’s Manual
dcread RT, RA,
RB
Read either tag or data information from the data cache
congruence class associated with the EA (RA|0) + (RB).
Place the results in RT.
9-57
iccci RA, RB Invalidate instruction cache. 9-67
icread RA, RB Read either tag or data information from the instruction
cache congruence class associated with the EA
(RA|0) + (RB).
Place the results in ICDBDR.
9-68
mfdcr RT, DCRN Move from DCR to RT,
(RT)
← (DCR(DCRN)).
9-110
mfmsr RT Move from MSR to RT,
(RT)
← (MSR).
9-111
mfspr RT, SPRN Move from SPR to RT,
(RT)
← (SPR(SPRN)).
Privileged for all SPRs except
LR, CTR, TBHU, TBLU, and XER.
9-112
mtdcr DCRN, RS Move to DCR from RS,
(DCR(DCRN))
← (RS).
9-117
mtmsr RS Move to MSR from RS,
(MSR)
← (RS).
9-118
mtspr SPRN, RS Move to SPR from RS,
(SPR(SPRN))
← (RS).
Privileged for all SPRs except
LR, CTR, and XER.
9-119
rfci Return from critical interrupt
(PC)
← (SRR2).
(MSR)
← (SRR3).
9-144
rfi Return from interrupt.
(PC)
← (SRR0).
(MSR)
← (SRR1).
9-145
tlbre RT,
RA,WS
If WS = 0:
Load TLBHI portion of the selected TLB entry into RT.
Load the PID register with the contents of the TID field of
the selected TLB entry.
(RT)
← TLBHI[(RA)]
(PID)
← TLB[(RA)]
TID
If WS = 1:
Load TLBLO portion of the selected TLB entry into RT.
(RT)
← TLBLO[(RA)]
9-184
Table B-4. Privileged Instructions (continued)
Mnemonic Operands Function
Other Registers
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