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1-10 PPC405 Core User’s Manual
The mtdcr and mfdcr instructions are privileged, for all DCRs. Therefore, all accesses to DCRs are
privileged. See “Privileged Mode Operation” on page 2-30.
All DCR numbers are reserved, and should be neither read nor written, unless they are part of an IBM
Core+ASIC implementation.
1.4.8 Addressing Modes
The processor core supports the following addressing modes, which enable efficient retrieval and
storage of data in memory:
• Base plus displacement addressing
• Indexed addressing
• Base plus displacement addressing and indexed addressing, with update
In the base plus displacement addressing mode, an effective address (EA) is formed by adding a
displacement to a base address contained in a GPR (or to an implied base of 0). The displacement is
an immediate field in an instruction.
In the indexed addressing mode, the EA is formed by adding an index contained in a GPR to a base
address contained in a GPR (or to an implied base of 0).
The base plus displacement and the indexed addressing modes also have a “with update” mode. In
“with update” mode, the effective address calculated for the current operation is saved in the base
GPR, and can be used as the base in the next operation. The “with update” mode relieves the
processor from repeatedly loading a GPR with an address for each piece of data, regardless of the
proximity of the data in memory.