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8-8 PPC405 Core User’s Manual
Figure 8-3. Debug Status Register (DBSR)
0 IC Instruction Completion Debug Event
0 Event did not occur
1 Event occurred
1 BT Branch Taken Debug Event
0 Event did not occur
1 Event occurred
2 EDE Exception Debug Event
0 Event did not occur
1 Event occurred
3 TIE Trap Instruction Debug Event
0 Event did not occur
1 Event occurred
4 UDE Unconditional Debug Event
0 Event did not occur
1 Event occurred
5 IA1 IAC1 Debug Event
0 Event did not occur
1 Event occurred
6 IA2 IAC2 Debug Event
0 Event did not occur
1 Event occurred
7 DR1 DAC1 Read Debug Event
0 Event did not occur
1 Event occurred
8 DW1 DAC1 Write Debug Event
0 Event did not occur
1 Event occurred
9 DR2 DAC2 Read Debug Event
0 Event did not occur
1 Event occurred
10 DW2 DAC2 Write Debug Event
0 Event did not occur
1 Event occurred
11 IDE Imprecise Debug Event
0 No circumstance that would cause a
debug event (if MSR[DE] = 1) occurred
1 A debug event would have occurred, but
debug exceptions were disabled
(MSR[DE] = 0)
01234567891011121314 21 22 23 24 31
IC
BT TIE IA1 DR1
EDE UDE DW1
MRR
IDE
IA2
DR2
DW2
IA3
IA4