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DBCR1
Debug Control Register 1
Register Summary 10-13
DBCR1
SPR 0x3BD
See “Debug Control Registers” on page 8-4.
Figure 10-6. Debug Control Register 1 (DBCR1)
0 D1R DAC1 Read Debug Event
0 Disabled
1 Enabled
1 D2R DAC 2 Read Debug Event
0 Disabled
1 Enabled
2 D1W DAC 1 Write Debug Event
0 Disabled
1 Enabled
3 D2W DAC 2 Write Debug Event
0 Disabled
1 Enabled
4:5 D1S DAC 1 Size
00 Compare all bits
01 Ignore lsb (least significant bit)
10 Ignore two lsbs
11 Ignore five lsbs
Address bits used in the compare:
Byte address
Halfword address
Word address
Cache line (8-word) address
6:7 D2S DAC 2 Size
00 Compare all bits
01 Ignore lsb (least significant bit)
10 Ignore two lsbs
11 Ignore five lsbs
Address bits used in the compare:
Byte address
Halfword address
Word address
Cache line (8-word) address
8 DA12 Enable Data Address Range Compare 1:2
0 Disabled
1 Enabled
Registers DAC1 and DAC2 define an
address range used for DAC address
comparisons
9 DA12X Data Address Exclusive Range Compare
1:2
0 Inclusive
1 Exclusive
Selects range defined by DAC1 and DAC2
to be inclusive or exclusive
10:11
Reserved
012345678910 11 12 13 14 15 16 19 20 23 24 31
D1R
D2R
D1W
D1S
D2S
DA12
DA12X
DV1M
DV1BE
DV2M
DV2BE
D2W