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About This Book xxi
About This Book
This user’s manual provides the architectural overview, programming model, and detailed information
about the registers, the instruction set, and operations of the IBM™ PowerPC™ 405 (PPC405 core)
32-bit RISC embedded processor core.
The PPC405 RISC embedded processor core features:
• PowerPC Architecture™
• Single-cycle execution for most instructions
• Instruction cache unit and data cache unit
• Support for little endian operation
• Interrupt interface for one critical and one non-critical interrupt signal
• JTAG interface
• Extensive development tool support
Who Should Use This Book
This book is for system hardware and software developers, and for application developers who need
to understand the PPC405 core. The audience should understand embedded processor design,
embedded system design, operating systems, RISC processing, and design for testability.
How to Use This Book
This book describes the PPC405 device architecture, programming model, external interfaces,
internal registers, and instruction set. This book contains the following chapters, arranged in parts:
Chapter 1 Overview
Chapter 2 Programming Model
Chapter 3 Initialization
Chapter 4 Cache Operations
Chapter 5 Fixed-Point Interrupts and Exceptions
Chapter 6 Timer Facilities
Chapter 7 Memory Management
Chapter 8 Debugging
Chapter 9 Instruction Set
Chapter 10 Register Summary
This book contains the following appendixes:
Appendix A Instruction Summary
Appendix B Instructions by Category
Appendix C Code Optimization and Instruction Timings