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Initialization 3-5
3.4 Initialization Code Example
The following initialization code illustrates the steps that should be taken to initialize the processor
before an operating system or user programs begin execution. The example is presented in pseudo-
code; function calls are named similarly to PPC405 mnemonics where appropriate. Specific
implementations may require different ordering of these sections to ensure proper operation.
/*—————————————————————————————————————— */
/* PPC405 Initialization Pseudo Code */
/*—————————————————————————————————————— */
@0xFFFFFFFC: /* initial instruction fetch from 0xFFFFFFFC */
ba(init_code); /* branch to initialization code */
@init_code:
/* ———————————————————————————————————— */
/* Configure guarded attribute for performance. */
/* ———————————————————————————————————— */
mtspr(SGR, guarded_attribute);
/* ———————————————————————————————————— */
/* Configure endianness and compression. */
/* ———————————————————————————————————— */
mtspr(SLER, endianness);
mtspr(SU0R, compression_attribute);
/* —————————————————————————*/
/* Invalidate the instruction cache and enable cachability —*/
/* —————————————————————————*/
iccci; /* invalidate i-cache */
mtspr(ICCR, i_cache_cachability); /* enable I-cache*/
isync;
/* ———————————————————————————————————— */
/* Invalidate the data cache and enable cachability */
/* ———————————————————————————————————— */
address = 0; /* start at first line */
for (line = 0; line <m_lines; line++) /* D-cache has m_lines congruence classes */
{
dccci(address); /* invalidate congruence class */
address += 32; /* point to the next congruence class */
}
mtspr(CCR0, store-miss_line-fill);
mtspr(DCWR, copy-back_write-thru);
mtspr(DCCR, d_cache_cachability); /* enable D-cache */
isync;
/* ———————————————————————————————————— */
/* Prepare system for synchronous interrupts. */
/* ———————————————————————————————————— */