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Instructions by Category B-43
tlbre RT, RA,WS If WS = 0:
Load TLBHI portion of the selected TLB entry into RT.
Load the PID register with the contents of the TID
field of the selected TLB entry.
(RT)
← TLBHI[(RA)]
(PID)
← TLB[(RA)]
TID
If WS = 1:
Load TLBLO portion of the selected TLB entry into
RT.
(RT)
← TLBLO[(RA)]
9-184
tlbsx RT,RA,RB Search the TLB array for a valid entry which
translates the EA
EA = (RA|0) + (RB).
If found,
(RT)
← Index of TLB entry.
If not found,
(RT) Undefined.
9-186
tlbsx. If found,
(RT)
← Index of TLB entry.
CR[CR0]
EQ
← 1.
If not found,
(RT) Undefined.
CR[CR0]
EQ
← 1.
CR[CR0]
LT,GT,SO
tlbsync tlbsync does not complete until all previous TLB-
update instructions executed by this processor have
been received and completed by all other processors.
For the PPC405 core, tlbsync is a no-op.
9-187
tlbwe RS, RA,WS If WS = 0:
Write TLBHI portion of the selected TLB entry from
RS.
Write the TID field of the selected TLB entry from the
PID register.
TLBHI[(RA)]
← (RS)
TLB[(RA)]
TID
← (PID)
24:31
If WS = 1:
Write TLBLO portion of the selected TLB entry from
RS.
TLBLO[(RA)]
← (RS)
9-188
Table B-14. TLB Management Instructions (continued)
Mnemonic Operands Function
Other Registers
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