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Instruction Summary A-17
lhzu RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and pad
left with zeroes,
(RT)
←
16
0 || MS(EA,2).
Update the base address,
(RA)
← EA.
9-81
lhzux RT, RA, RB Load halfword from EA = (RA|0) + (RB) and pad left
with zeroes,
(RT)
←
16
0 || MS(EA,2).
Update the base address,
(RA)
← EA.
9-82
lhzx RT, RA, RB Load halfword from EA = (RA|0) + (RB) and pad left
with zeroes,
(RT)
←
16
0 || MS(EA,2).
9-83
li RT, IM Load immediate.
(RT)
← EXTS(IM)
Extended mnemonic for
addi RT,0,value
9-9
lis RT, IM Load immediate shifted.
(RT)
← (IM ||
16
0)
Extended mnemonic for
addis RT,0,value
9-12
lmw RT, D(RA) Load multiple words starting from
EA = (RA|0) + EXTS(D).
Place into consecutive registers RT through GPR(31).
RA is not altered unless RA = GPR(31).
9-84
lswi RT, RA, NB Load consecutive bytes from EA=(RA|0).
Number of bytes n=32 if NB=0, else n=NB.
Stack bytes into words in CEIL(n/4)
consecutive registers starting with RT, to
R
FINAL
← ((RT + CEIL(n/4) – 1) % 32).
GPR(0) is consecutive to GPR(31).
RA is not altered unless RA = R
FINAL
.
9-85
lswx RT, RA, RB Load consecutive bytes from EA=(RA|0)+(RB).
Number of bytes n=XER[TBC].
Stack bytes into words in CEIL(n/4)
consecutive registers starting with RT, to
R
FINAL
← ((RT + CEIL(n/4) – 1) % 32).
GPR(0) is consecutive to GPR(31).
RA is not altered unless RA = R
FINAL
.
RB is not altered unless RB = R
FINAL
.
If n=0, content of RT is undefined.
9-87
lwarx RT, RA, RB Load word from EA = (RA|0) + (RB) and place in RT,
(RT)
← MS(EA,4).
Set the Reservation bit.
9-89
lwbrx RT, RA, RB Load word from EA = (RA|0) + (RB) then reverse byte
order,
(RT)
← MS(EA+3,1) || MS(EA+2,1) ||
MS(EA+1,1) || MS(EA,1).
9-90
Table A-1. PPC405 Instruction Syntax Summary (continued)
Mnemonic Operands Function
Other Registers
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