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4-2 PPC405 Core User’s Manual
The PPC405 core can include an instruction cache array and a data cache array. The size of the
cache arrays can vary by core implementation, as shown in Table 4-1.
Programming Note: If the ICU cache array or the DCU cache array is not present (0KB), the I
(cachability) storage attribute must be turned off for instruction-side or data-side memory,
respectively.
“ICU and DCU Organization and Sizes” describes the organization and sizes of the ICU and the DCU.
“ICU Overview” on page 4-3 and “DCU Overview” on page 4-6 provide overviews of the ICU and
DCU.
4.1 ICU and DCU Organization and Sizes
The ICU and DCU contain control logic and, in some implementations, cache arrays. The control
logic, which handles data transfers between the cache units, main memory, and the RISC core, differs
significantly between the ICU and DCU. The ICU and DCU cache arrays, which (when implemented)
store instructions and data from main memory, respectively, are almost identical. (The DCU array
adds a “dirty” bit to mark modified lines.)
The ICU and DCU cache arrays are two-way set-associative. In both cache units, a cache line can be
in one of two locations in the cache array. The two locations are members of a set of locations. Each
set is divided into two ways, way A and way B; a cache line can be located in either way. Each way is
organized as
n
lines of eight words each, where
n
is the cache size, in kilobytes, multiplied by 16. For
example, a 4KB cache array contains 64 lines.
Cache lines are addressed using a tag field and an index. The tag fields are also two-way set-
associative. As shown in Table 4-2, the tag fields in ways A and B store address bits A
0:
2
1
for each
Table 4-1. Available Cache Array Sizes
ICU Cache Array Size DCU Cache Array Size
0KB 0KB
4KB 4KB
8KB 8KB
16KB 16KB
32KB 32KB