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4-6 PPC405 Core User’s Manual
In practice, cache synonyms occur when a real instruction page having multiple virtual mappings
exists in multiple cache lines. For 1KB pages, all EAs differing in EA
19:21
must be cast out of cache,
using an icbi instruction for each such EA (up to 8 per cache line in the page). For 4KB pages, all EAs
differing in EA
19
must be cast out in the same manner (up to 2 per cache line in the page). For larger
pages, cache synonyms do not occur, and casting out any of the multiple EAs removes the physical
information from the cache.
Programming Note: To prevent the occurrence of cache synonyms, use only page sizes greater
than the cache way size (8KB), if possible. For the PPC405, the minimum such page size is 16KB.
4.2.4 ICU Coherency
The ICU does not “snoop” external memory or the DCU. Programmers must follow special
procedures for ICU synchronization when self-modifying code is used or if a peripheral device
updates memory containing instructions.
The following code example illustrates the necessary steps for self-modifying code. This example
assumes that
addr1
is both data and instruction cachable.
stw regN, addr1 # the data in regN is to become an instruction at addr1
dcbst addr1 # forces data from the data cache to memory
sync # wait until the data actually reaches the memory
icbi addr1 # the previous value at addr1 might already be in
the instruction cache; invalidate it in the cache
isync # the previous value at addr1 may already have been
pre-fetched into the queue; invalidate the queue
so that the instruction must be re-fetched
4.3 DCU Overview
The DCU manages data transfers between external cachable memory and the general-purpose
registers in the execution unit.
A bypass path handles data operations in cache-inhibited memory and improves performance during
line fill operations.
4.3.1 DCU Operations
Data from cachable memory regions are copied from external memory into lines in the data cache
array so that subsequent cache operations result in cache hits. Loads and stores that hit in the DCU
are completed in one cycle. For loads, GPRs receive the requested byte, halfword, or word of data
from the data cache array. The DCU supports byte-writeability to improve the performance of byte and
halfword store operations.
Cache operations require a line fill when they require data from cachable memory regions that are not
currently in the DCU. A line fill is the movement of a cache line (eight words) from external memory to
the data cache array. Eight words are copied from external memory into the fill buffer, either target-
word-first or sequentially, or in any other order. Loading order is controlled by the PLB slave. Target-
word-first fills start at the requested word, continue to the end of the line, and then wrap to fill the
remaining words at the beginning of the line. Sequential fills start at the first word of the cache line