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Memory Management 7-17
the operand address of the instruction). To restrict possible damage from an instruction which can
change data and yet avoids the protection mechanism, the dccci instruction is privileged.
If data address translation is enabled, dccci can cause data storage interrupts when
TLB_entry[WR] = 0; the operand is treated as if it were address-specific. dccci cannot cause a data
storage interrupt when ZPR[Z
n
] = 00, because it is a privileged instruction.
Because dccci can cause data storage and TLB -miss interrupts, use of dccci is not recommended
when MSR[DR] = 1; if dccci is used. Note that the specific operand address can cause an interrupt.
Architecturally, dcbt and dcbtst are treated as “loads” because they do not change data; they cannot
cause data storage interrupts when TLB_entry[WR] = 0.
The cache block touch instructions dcbt and dcbtst are considered “speculative” loads; therefore, if a
data storage interrupt would otherwise result from the execution of dcbt or dcbtst when
ZPR[Z
n
] = 00, the instruction is treated as a no-op and the interrupt does not occur. Similarly, TLB
miss interrupts do not occur for these instructions.
Architecturally, dcbf and dcbst are treated as “loads”. Flushing or storing a line from the cache is not
architecturally considered a “store” because a store was performed to update the cache, and dcbf or
dcbst only update main memory. Therefore, neither dcbf nor dcbst can cause data storage
interrupts when TLB_entry[WR] = 0. Because neither instruction is privileged, they can cause data
storage interrupts when ZPR[Z
n
] = 00 and data address translation is enabled.
dcread is a “load” from a non-specific address, and is privileged. Therefore, it cannot cause data
storage interrupts when ZPR[Z
n
] = 00 or TLB_entry[WR] = 0.
icbi and icbt are considered “loads” and cannot cause data storage interrupts when
TLB_entry[WR] = 0. icbi can cause data storage interrupts when ZPR[Z
n
] = 00.
The iccci instruction cannot change data; an instruction cache line cannot be dirty. The iccci
instruction is privileged and is considered a load. It does not cause data storage interrupts when
ZPR[Z
n
] = 00 or TLB_entry[WR] = 0.
Because iccci can cause a TLB miss interrupt, using iccci is not recommended when data address
translation is enabled; if it is used, note that the specific operand address can cause an interrupt.
icread is considered a “load” from a non-specific address, and is privileged. Therefore, it cannot
cause data storage interrupts when ZPR[Z
n
] = 00 or TLB_entry[WR] = 0.
7.7.3 Access Protection for String Instructions
The stswx instruction with string length equal to 0(XER[TBC] = 0) is a no-op.
When data address translation is enabled and the Transfer Byte Count (TBC) field of the Fixed Point
Exception Register (XER) is 0, neither lswx nor stswx can cause TLB miss interrupts, or data
storage interrupts when ZPR[Z
n
] = 0 or TLB_entry[WR] = 0.
7.8 Real-Mode Storage Attribute Control
The PowerPC Architecture and the PowerPC Embedded Environment define several SPRs to control
the following storage attributes in real mode: W, I, G,U0, and E. Note that the U0 and E attributes are
not defined in the PowerPC Architecture. The E attribute is defined in the IBM PowerPC Embedded
Environment, and the U0 attribute is implementation-specific. No storage attribute control register is