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10-4 PPC405 Core User’s Manual
10.6 Time Base Registers
The PowerPC Architecture provides a 64-bit time base. Chapter 6, “Timer Facilities,” describes the
architected time base. In the PPC405 core, the time base is implemented as two 32-bit time base
registers (TBRs). The low-order 32 bits of the time base are read from the TBL and the high-order 32
bits are read from the TBL.
User-mode access to the TBRs is read-only, and there is no explicitly privileged read access to the
time base.
The mftb instruction reads from TBL and TBU. (Writing the time base is accomplished by moving the
contents of a GPR to a pair of SPRs, which are also called TBL and TBU, using the mtspr
instruction.)
Table 10-3 shows the mnemonics, names, and numbers of the TBRs. The columns under “TBRN” list
the register numbers used as operands in assembler language coding of the mftb and mtspr
instructions. The column labeled “TBRF” lists the corresponding fields contained in the
machine code
of mftb and mtspr. The TBRN field contains two five-bit subfields of the TBRF field; the subfields are
reversed
in the machine code for the mftb and mtspr instructions (TBRN ← TBRF
5:9
|| TBRF
0:4
).
Note that the assembler handles the special coding transparently.
10.7 Device Control Registers
Device Control Registers (DCRs), which are architecturally outside of the processor core, are
accessed using the mfdcr and mtdcr instructions. DCRs are used to control, configure, and hold
status for various functional units that are not part of the RISC processor core. Although the PPC405
core does not contain DCRs, the mfdcr and mtdcr instructions are provided.
The mfdcr and mtdcr instructions are privileged, for all DCR numbers. Therefore, all DCR accesses
are privileged. All DCR numbers are reserved, and should be neither read nor written, unless they are
part of a Core+ASIC implementation.
Table 10-3. Time Base Registers
Mnemonic Register Name
TBRN
TBRF AccessDecimal Hex
TBL Time Base Lower (Read-only) 268 0x10C 0x188 Read-only
TBU Time Base Upper (Read-only) 269 0x10D 0x1A8 Read-only