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4-14 PPC405 Core User’s Manual
In the following sample code, registers RN, RM, RX, and RZ are any available GPRs.
! SEQUENCE 2 Alter CCR0[DPP1, U0XE)
! Turn off interrupts
mfmsr RM
addis RZ,r0,0x0002 ! CE bit
ori RZ,RZ,0x8000 ! EE bit
andc RZ,RM,RZ ! Turn off MSR[CE,EE]
mtmsr RZ
! sync
sync
! Alter CCR0 bits
mfspr RN,CCR0 ! Read CCR0.
andi/ori RN,RN,0xXXXX ! Execute and/or function to change any CCR0 bits.
mtspr CCR0, RN ! Update CCR0.
isync ! Refetch instructions under new processor context.
! Restore MSR to original value
mtmsr RM
CCR0[CIS, CWS] do not require special programming.
4.5.2 ICU Debugging
The icread instruction enables the reading of the instruction cache entries for the congruence class
specified by EA
18:26
, unless no cache array is present. The cache information is read into the
ICDBDR; from there it can subsequently be moved, using a mfspr instruction, into a GPR.
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR)
0:31 Instruction cache information See icread, page -68.
0 31