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Contents ix
Real-Mode Storage Attribute Control ............................................................................................................. 7-17
Storage Attribute Control Registers ........................................................................................................... 7-19
Data Cache Write-through Register (DCWR) ....................................................................................... 7-19
Data Cache Cachability Register (DCCR) ............................................................................................ 7-20
Instruction Cache Cachability Register (ICCR) ..................................................................................... 7-20
Storage Guarded Register (SGR) ......................................................................................................... 7-20
Storage User-defined 0 Register (SU0R) ............................................................................................. 7-20
Storage Little-Endian Register (SLER) ................................................................................................. 7-20
Chapter 8. Debugging ............................................................................................................8-1
Development Tool Support .............................................................................................................................. 8-1
Debug Modes ................................................................................................................................................... 8-1
Internal Debug Mode ................................................................................................................................... 8-1
External Debug Mode .................................................................................................................................. 8-2
Debug Wait Mode ........................................................................................................................................ 8-2
Real-time Trace Debug Mode ..................................................................................................................... 8-3
Processor Control ............................................................................................................................................ 8-3
Processor Status .............................................................................................................................................. 8-4
Debug Registers .............................................................................................................................................. 8-4
Debug Control Registers ............................................................................................................................. 8-4
Debug Control Register 0 (DBCR0) ........................................................................................................ 8-4
Debug Control Register1 (DBCR1) ......................................................................................................... 8-6
Debug Status Register (DBSR) .................................................................................................................. 8-7
Instruction Address Compare Registers (IAC1–IAC4) ................................................................................ 8-9
Data Address Compare Registers (DAC1–DAC2) .................................................................................... 8-9
Data Value Compare Registers (DVC1–DVC2) ........................................................................................8-10
Debug Events ............................................................................................................................................ 8-10
Instruction Complete Debug Event ............................................................................................................ 8-11
Branch Taken Debug Event ...................................................................................................................... 8-11
Exception Taken Debug Event .................................................................................................................. 8-11
Trap Taken Debug Event .......................................................................................................................... 8-12
Unconditional Debug Event ....................................................................................................................... 8-12
IAC Debug Event ....................................................................................................................................... 8-12
IAC Exact Address Compare ................................................................................................................ 8-12
IAC Range Address Compare .............................................................................................................. 8-12
DAC Debug Event ..................................................................................................................................... 8-13
DAC Exact Address Compare .............................................................................................................. 8-13
DAC Range Address Compare ............................................................................................................. 8-14
DAC Applied to Cache Instructions ....................................................................................................... 8-15
DAC Applied to String Instructions ........................................................................................................ 8-16
Data Value Compare Debug Event ........................................................................................................... 8-16
Imprecise Debug Event ............................................................................................................................. 8-19
Debug Interface ............................................................................................................................................. 8-19
IEEE 1149.1 Test Access Port (JTAG Debug Port) ..................................................................................8-19
JTAG Connector ............................................................................................................................................ 8-20
JTAG Instructions ...................................................................................................................................... 8-21
JTAG Boundary Scan ................................................................................................................................ 8-21
Trace Port ...................................................................................................................................................... 8-22
Chapter 9. Instruction Set .....................................................................................................9-1
Instruction Set Portability ................................................................................................................................. 9-1
Instruction Formats .......................................................................................................................................... 9-2
Pseudocode ..................................................................................................................................................... 9-2
Operator Precedence .................................................................................................................................. 9-5
Register Usage ................................................................................................................................................ 9-5
Alphabetical Instruction Listing ........................................................................................................................ 9-5
add .............................................................................................................................................................. 9-6