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1-2 PPC405 Core User’s Manual
– Instruction cache unit (ICU) non-blocking during line fills, data cache unit (DCU) non-blocking
during line fills and flushes
– Read and write line buffers
– Instruction fetch hits are supplied from line buffer
– Data load/store hits are supplied to line buffer
– Programmable ICU prefetching of next sequential line into line buffer
– Programmable ICU prefetching of non-cacheable instructions, full line (eight words) or half line
(four words)
– Write-back or write-through DCU write strategies
– Programmable allocation on loads and stores
– Operand forwarding during cache line fills
• Memory Management
– Translation of the 4GB logical address space into physical addresses
– Independent enabling of instruction and data translation/protection
– Page level access control using the translation mechanism
– Software control of page replacement strategy
– Additional control over protection using zones
– WIU0GE (write-through, cachability, compresseduser-defined 0, guarded, endian) storage
attribute control for each virtual memory region
• WIU0GE storage attribute control for thirty-two real 128MB regions in real mode
• Support for OCM that provides memory access performance identical to cache hits
• Full PowerPC floating-point unit (FPU) support using the auxiliary processor unit (APU) interface
(the PPC405 does not include an FPU)
• PowerPC timer facilities
– 64-bit time base
– PIT, FIT, and watchdog timers
– Synchronous external time base clock input
• Debug Support
– Enhanced debug support with logical operators
– Four instruction address compares (IACs)
– Two data address compares (DACs)
– Two data value compares (DVCs)
– JTAG instruction to write to ICU
– Forward or backward instruction tracing
• Minimized interrupt latency
• Advanced power management support