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Debugging 8-3
In this mode, access to the processor is through the JTAG debug port.
8.2.4 Real-time Trace Debug Mode
Real-time trace debug mode supports the generation of trigger events for tracing the instruction
stream being executed out of the instruction cache in real-time. In this mode, debug events can be
used to control the collection of trace information through the use of trigger event generation. The
broadcast of trace information is independent of the use of debug events as trigger events.This mode
does not alter the processor performance.
A trace event occurs when internal and external debug modes are disabled (DBCR0[IDM, EDM] = 0)
and a debug events occurs.
When a trace event occurs, a trace device can capture trace signals that provide the instruction trace
information. Most trace events generated from debug events are blocked when internal debug,
external debug, or debug wait modes are enabled
8.3 Processor Control
The PPC405 provides the following debug functions for processor control. Not all facilities are
available in all debug modes.
Instruction Step The processor is stepped one instruction at a time, while stopped, using the
JTAG debug port.
Instruction Stuff While the processor is stopped, instructions can be stuffed into the processor
and executed using the JTAG debug port.
Halt The processor can be stopped by activating an external halt signal on an
external event, such as a logic analyzer trigger. This signal freezes the
processor architecturally. While frozen, normal instruction execution stops and
architected processor resources can be accessed and altered using the JTAG
debug port. Normal execution resumes when the halt signal is deactivated.
Stop The processor can be stopped using the JTAG debug port. Activating a stop
causes the processor to become architecturally frozen. While frozen, normal
instruction execution stops and the architected processor resources can be
accessed and altered using the JTAG debug port.
Reset An external reset signal, the JTAG debug port, or DBCR0 can request core,
chip, and system resets.
Debug Events A debug event triggers a debug operation. The operation depends on the
debug mode. For more information and a list of debug events, see “Debug
Events” on page 8-10.
Freeze Timers The JTAG debug port or DBCR0 can control timer resources. The timers can
be enabled to run, freeze always, or freeze on a debug event.
Trap Instructions The trap instructions tw and twi can be used, with debug events, to implement
software breakpoints.