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Memory Management 7-13
The PPC405 does not provide hardware reference or change bits, but TLB miss interrupts and data
storage interrupts enable system software to maintain reference information for TLB entries and their
associated pages, respectively.
A possible algorithm follows. First, the TLB entries are built, with each TLB_entry[V, WR] = 0. System
software retains the index and EPN of each entry.
The first attempt by application code to access a page causes a TLB miss interrupt, because its TLB
entry is marked invalid. The TLB miss handler records the reference to the TLB entry (and to the
associated page) in a data structure, then sets TLB_entry[V] = 1. (Note that TLB_entry[V] can be
considered a reference bit for the TLB entry.) Subsequent read accesses to the page associated with
the TLB entry proceed normally.
In the example just given for recording TLB entry references, the first write access to the page using
the TLB entry, after the entry is made valid, causes a data storage interrupt because write access was
turned off. The TLB miss handler records the write to the page in a data structure, for use as a
“changed” flag, then sets TLB_entry[WR] = 1 to enable write access. (Note that TLB_entry[WR] can
be considered a change bit for the page.) Subsequent write accesses to the page proceed normally.
7.7 Access Protection
The PPC405 provides virtual-mode access protection. The TLB entry enables system software to
control general access for programs in the problem state, and control write and execute permissions
for all pages. The TLB entry can specify zone protection that can override the other access control
mechanisms supported in the TLB entries.
TLB entry and zone protection methods also support access controls for cache operation and string
loads/stores.
7.7.1 Access Protection Mechanisms in the TLB
For MMU access protection to be in effect, one or both of MSR[IR] or MSR[DR] must be set to one to
enable address translation. MSR[IR] enables protection on instruction fetches, which are inherently
read-only. MSR[DR] enables protection on data accesses (loads/stores).
7.7.1.1 General Access Protection
The translation ID (TLB_entry[TID]) provides the first level of MMU access protection. This 8-bit field,
if non-zero, is compared to the contents of TLB_entry[PID]. These fields must match in a valid TLB
entry if any access is to be allowed. In typical use, it is assumed that a program in the supervisor
state, such as a real-time operating system, sets the PID before starting a problem state program that
is subject to access control.