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9-4 PPC405 Core User’s Manual
xx Bit positions which are don’t-cares.
CEIL(x) Least integer ≥ x.
EXTS(x) The result of extending
x
on the left with sign bits.
PC Program counter.
RESERVE Reserve bit; indicates whether a process has reserved a block of
storage.
CIA Current instruction address; the 32-bit address of the instruction being
described by a sequence of pseudocode. This address is used to set the
next instruction address (NIA). Does not correspond to any architected
register.
NIA Next instruction address; the 32-bit address of the next instruction to be
executed. In pseudocode, a successful branch is indicated by assigning
a value to NIA. For instructions that do not branch, the NIA is CIA +4.
MS(addr, n) The number of bytes represented by
n
at the location in main storage
represented by
addr
.
EA Effective address; the 32-bit address, derived by applying indexing or
indirect addressing rules to the specified operand, that specifies an
location in main storage.
EA
b
A bit in an effective address.
EA
b:b
A range of bits in an effective address.
ROTL((RS),n) Rotate left; the contents of RS are shifted left the number of bits
specified by
n
.
MASK(MB,ME) Mask having 1s in positions MB through ME (wrapping if MB > ME) and
0s elsewhere.
instruction(EA) An instruction operating on a data or instruction cache block associated
with an EA.