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Programming Model 2-5
2.3.1 General Purpose Registers (R0-R31)
The PPC405 core contains thirty-two 32-bit general purpose registers (GPRs). Data from memory
can be read into GPRs using load instructions and the contents of GPRs can be written to memory
using store instructions. Most integer instructions use GPRs for source and destination operands.
See Table 10, “Register Summary,” on page 10-1 for the numbering of the GPRs.
2.3.2 Special Purpose Registers
Special purpose registers (SPRs), which are part of the PowerPC Architecture and the IBM PowerPC
Embedded Environment, are accessed using the mtspr and mfspr instructions.
SPRs control the operation of debug facilities, timers, interrupts, storage control attributes, and other
architected processor resources. Table 10, “Register Summary,” on page 10-1 shows the mnemonic,
name, and number for each SPR. Table 2-1, “PPC405 SPRs,” on page 2-6 lists the PPC405 SPRs by
function and indicates the pages where the SPRs are described more fully.
Except for the Link Register (LR), the Count Register (CTR), the Fixed-point Exception Register
(XER), User SPR General 0 (USPRG0, and read access to SPR General 4–7 (SPRG4–SPRG7), all
SPRs are privileged. As SPRs, the registers TBL and TBU are privileged write-only; as TBRs, these
registers can be read in user mode. Unless used to access non-privileged SPRs, attempts to execute
mfspr and mtspr instructions while in user mode cause privileged violation program interrupts. See
“Privileged SPRs” on page 2-32.
Figure 2-2. General Purpose Registers (R0-R31)
0:31 General Purpose Register data
0 31