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4-8 PPC405 Core User’s Manual
write-through is enabled and caching is inhibited.
4.3.3 DCU Load and Store Strategies
The DCU can control whether a load receives one word or one line of data from main memory.
For cachable memory, the load without allocate (LWOA) field of the CCR0 controls the type of load
resulting from a load miss. If CCR0[LWOA] = 0, a load miss causes a line fill. If CCR0[LWOA] = 1,
load misses do not result in a line fill, but in a word load from external memory. For infrequent reads of
non-contiguous memory, setting CCR0[LWOA] = 1 may provide a small performance improvement.
For non-cachable memory and for loads misses when CCR0[LWOA] = 1, the load word as line (LWL)
field in the CCR0 affects whether load misses are satisfied with a word, or with eight words (the
equivalent of a cache line) of data. If CCR0[LWL] = 0, only the target word is bypassed to the core. If
CCR0[LWL] = 1, the DCU saves eight words (one of which is the target word) in the fill buffer and
bypasses the target data to the core to satisfy the load word request. The fill buffer is not written to the
data cache array.
Setting CCR0[LWL] = 1 provides the fastest accesses to sequential non-cachable memory.
Subsequent loads from the same line are bypassed to the core from the fill buffer and do not result in
additional external memory accesses. The load data remains valid in the fill buffer until one of the
following occurs: the beginning of a subsequent load that requires the fill buffer, a store to the target
address, a dcbi or dccci instruction issued to the target address, or the execution of a sync
instruction. Non-cachable loads to guarded storage never cause a line transfer on the PLB even if
CCR0[LWL] = 1. Subsequent loads to the same non-cachable storage are always requested again
from the PLB.
For cachable memory, the store without allocate (SWOA) field of the CCR0 controls the type of store
resulting from a store miss. If CCR0[SWOA] = 0, a store miss causes a line fill. If CCR0[SWOA] = 1,
store misses do not result in a line fill, but in a single word store to external memory.
4.3.4 Data Cachability Control
When data address translation is disabled (MSR[DR] = 0), data cachability is controlled by the Data
Cache Cachability Register (DCCR). Each bit in the DCCR (DCCR[S0:S31]) controls the cachability
of a 128MB region (see “Real-Mode Storage Attribute Control” on page 7-17). If DCCR[S
n
]=1,
caching is enabled for the specified region; otherwise, caching is inhibited.
When data address translation is enabled (MSR[DR] = 1), data cachability is controlled by the I bit in
the TLB entry for the memory page. If TLB_entry[I] = 1, caching is inhibited; otherwise caching is
enabled. Cachability is controlled separately for each page, which can range in size from 1KB to
16MB. “Translation Lookaside Buffer (TLB)” on page 7-2 describes the TLB.
Programming Note: The PowerPC Architecture does not support memory models in which
write-through is enabled and caching is inhibited.
The performance of the PPC405 core is significantly lower while accessing memory in cache-
inhibited regions.
Following system reset, address translation is disabled and all DCCR bits are reset to 0 so that no
memory regions are cachable. If an array is present, the dccci instruction must execute
n
times
before regions can be designated as cachable. This invalidates all congruence classes before