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8-2 PPC405 Core User’s Manual
To enable internal debug mode, the Debug Control Register 0 (DBCR0) field IDM is set to 1
(DBCR0[IDM] = 1). To enable debug interrupts, MSR[DE] = 1. A debug interrupt occurs on a debug
event only if DBCR0[IDM] = 1 and MSR[DE] = 1.
8.2.2 External Debug Mode
External debug mode provides access to architected processor resources and supports stopping,
starting, and stepping the processor, setting hardware and software breakpoints, and monitoring
processor status. In this mode, debug events cause the processor to become architecturally frozen.
While the processor is frozen, normal instruction execution stops and architected processor
resources can be accessed and altered. External bus activity continues in external debug mode.
The JTAG mechanism can pass instructions to the processor for execution, allowing a JTAG debugger
to display and alter processor resources, including memory.
The JTAG mechanism prevents the occurrence of a privileged exception when a privileged instruction
is executed while the processor is in user mode.
Storage access control by a memory management unit (MMU) remains in effect while in external
debug mode; the debugger may need to modify MSR or TLB values to access protected memory.
Because external debug mode relies only on internal processor resources, it can be used to debug
system hardware and software.
In this mode, access to the processor is through the JTAG debug port.
To enable external debug mode, DBCR0[EDM] = 1. To enable debug interrupts, MSR[DE] = 1. A
debug interrupt occurs on a debug event only if DBCR0[EDM] = 1 and MSR[DE] = 1.
8.2.3 Debug Wait Mode
In debug wait mode, debug events cause the PPC405 to enter a state in which interrupts can be
serviced while the processor appears to be stopped.
Debug wait mode provides access to architected processor resources in a manner similar to external
debug mode, except that debug wait mode allows the servicing of interrupt handlers. It supports
stopping, starting, and stepping the processor, setting hardware and software breakpoints, and
monitoring processor status. In this mode, if a debug event caused the processor to become
architecturally frozen, an interrupt causes the processor to run an interrupt handler and return to the
architecturally frozen state upon returning from the interrupt handler. While the processor is frozen,
normal instruction execution stops and architected processor resources can be accessed and altered.
External bus activity continues in debug wait mode.
The processor enters debug wait mode when internal and external debug modes are disabled
(DBCR0[IDM, EDM] = 0), debug wait mode is enabled (MSR[DWE] = 1), debug wait is enabled by the
JTAG debugger, and a debug event occurs.
For example, while the PPC405 core is in debug wait mode, an external device might generate an
interrupt that requires immediate service. The PPC405 core can service the interrupt (vector to an
interrupt handler and execute the interrupt handler code) and return to the previous stopped state.
Debug wait mode relies only on internal processor resources, so it can be used to debug both system
hardware and software problems. This mode can also be used for software development on systems
without a control program, or to debug control program problems.