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Instruction Set 9-171
stwcx.
Store Word Conditional Indexed
stwcx.
Store Word Conditional Indexed
EA ← (RA|0) + (RB)
if RESERVE = 1 then
MS(EA, 4)
← (RS)
RESERVE
← 0
(CR[CR0])
←
2
0 || 1 || XER
so
else
(CR[CR0])
←
2
0 || 0 || XER
so
An effective address (EA) is formed by adding an index to a base address. The index is the contents
of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA
otherwise.
If the reservation bit contains 1 when the instruction is executed, the contents of register RS are
stored into the word at the EA and the reservation bit is cleared. If the reservation bit contains 0 when
the instruction is executed, no store operation is performed.
CR[CR0] is set as follows:
• CR[CR0]
LT, GT
are cleared
• CR[CR0]
EQ
is set to the state of the reservation bit at the start of the instruction
• CR[CR0]
SO
is set to the contents of the XER[SO] bit
Registers Altered
• CR[CR0]
LT, GT, EQ, SO
Programming Note
lwarx and the stwcx. instruction should paired in a loop, as shown in the following example, to create
the effect of an atomic operation to a memory area used as a semaphore between asynchronous
processes. Only lwarx can set the reservation bit to 1. stwcx. sets the reservation bit to 0 upon its
completion, whether or not stwcx. sent (RS) to memory. CR[CR0]
EQ
must be examined to determine
whether (RS) was sent to memory.
loop: lwarx # read the semaphore from memory; set reservation
“alter” # change the semaphore bits in register as required
stwcx. # attempt to store semaphore; reset reservation
bne loop # an asynchronous process has intervened; try again
If the asynchronous process in the code example had paired lwarx with a store other than stwcx., the
reservation bit would not have been cleared in the asynchronous process, and the code example
would have overwritten the semaphore.
Exceptions
An alignment exception occurs if the EA is not word-aligned.
stwcx. RS, RA, RB
31 RS RA RB 150
0 6 11 16 21 31