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5-2 PPC405 Core User’s Manual
3. The instruction having its address reported to the interrupt handler may appear not to have begun
execution, or may have partially completed.
Synchronous
interrupts are caused directly by the execution (or attempted execution) of instructions.
Synchronous interrupts can be either precise or imprecise.
For synchronous precise interrupts, the following rules apply:
1. The save/restore register addresses either the instruction causing the exception or the next
sequential instruction. Which instruction is addressed is determined by the interrupt type and
status bits.
2. All instructions preceding the instruction causing the exception have completed execution.
However, some storage accesses generated by these preceding instructions may not have
completed.
3. The instruction causing the exception may appear not to have begun execution (except for causing
the exception), may have partially completed, or may have completed, depending on the interrupt
type.
4. No subsequent instruction has begun execution.
Refer to
IBM PowerPC Embedded Environment
for an architectural description of imprecise
interrupts.
Machine check
interrupts are a special case typically caused by some kind of hardware or storage
subsystem failure, or by an attempt to access an invalid address. A machine check can be indirectly
caused by the execution of an instruction, but not recognized or reported until long after the processor
has executed past the instruction that caused the machine check. As such, machine check interrupts
cannot properly be thought of as synchronous, nor as precise or imprecise. For machine checks, the
following general rules apply:
1. No instruction following the one whose address is reported to the machine check handler in the
save/restore register has begun execution.
2. The instruction whose address is reported to the machine check handler in the save/restore
register, and all previous instructions, may or may not have completed successfully. All previous
instructions that would ever complete have completed, within the context existing before the
machine check interrupt. No further interrupt (other than possible additional machine checks) can
occur as a result of those instructions.
5.2 Behavior of the PPC405 Processor Core Implementation
All interrupts, except for machine checks, are handled precisely. Precise handling implies that the
address of the excepting instruction (for synchronous exceptions other than the system call
exception), or the address of the next instruction to be executed (asynchronous exceptions and the
system call exception), is passed to an interrupt handling routine. Precise handling also implies that
all instructions that precede the instruction whose address is reported to the interrupt handling routine
have executed and that no subsequent instruction has begun execution. The specific instruction
whose address is reported may not have begun execution or may have partially completed, as
specified for each precise interrupt type.