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Instruction Set 9-1
Chapter 9. Instruction Set
Descriptions of the PPC405 instructions follow. Each description contains the following elements:
• Instruction names (mnemonic and full)
• Instruction syntax
• Instruction format diagram
• Pseudocode description
• Prose description
• Registers altered
• Architecture notes identifying the associated PowerPC Architecture component
Where appropriate, instruction descriptions list invalid instruction forms and exceptions, and provide
programming notes.
9.1 Instruction Set Portability
To support embedded real-time applications, the instruction sets of the PPC405 core and other IBM
controllers implement the IBM PowerPC Embedded Environment, which is not part of the PowerPC
Architecture defined in
The PowerPC Architecture: A Specification for a New Family of RISC
Processors
.
Programs using these instructions are not portable to PowerPC implementations that do not
implement the IBM PowerPC Embedded Environment.
The PPC405 core implements a number of implementation-specific instructions that are not part of
the PowerPC Architecture or the IBM PowerPC Embedded Environment, which are listed in Table 9-1.
In the table, the syntax “[o]” indicates that an instruction has an “o” form, which updates the
XER[SO,OV] fields, and a “non-o” form. The syntax “[.]” indicates that an instruction has a “record”
form, which updates CR[CR0], and a “non-record” form.
Table 9-1. Implementation-Specific Instructions
dccci
dcread
iccci
icread
macchw[o][.]
macchws[o][.]
macchwsu[o][.]
macchwu[o][.]
machhw[o][.]
machhws[o][.]
machhwsu[o][.]
machhwu[o][.]
maclhw[o][.]
maclhws[o][.]
maclhwsu[o][.]
maclhwu[o][.]
mfdcr
mtdcr
mulchw[.]
mulchwu[.]
mulhhw[.]
mulhhwu[.]
mullhw[.]
mullhwu[.]
nmacchw[o][.]
nmacchws[o][.]
nmachhw[o][.]
nmachhws[o][.]
nmaclhw[o][.]
nmaclhws[o][.]
rfci
tlbre
tlbsx[.]
tlbwe
wrtee
wrteei