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Index
Index
A
AA field
conditional branches 2-24
unconditional branches 2-24
access protection
cache instructions 7-16
string instructions 7-17
virtual mode 7-13
add 9-6
add. 9-6
addc 9-7
addc. 9-7
addco 9-7
addco. 9-7
adde 9-8
adde. 9-8
addeo 9-8
addeo. 9-8
addi 9-9
addic 9-10
addic. 9-11
addis 9-12
addme 9-13
addme. 9-13
addmeo 9-13
addmeo. 9-13
addo 9-6
addo. 9-6
address translation
illustrated 7-2
MMU 7-1
relationship between TLBs, illustrated 7-9
addressing modes 1-10
addze 9-14
addze. 9-14
addzeo 9-14
addzeo. 9-14
alignment
for cache control instructions 2-16
for storage reference instructions 2-16
of data types 2-16
alignment interrupts
causes of 2-17
register settings 5-19
summary 5-19
and 9-15
and. 9-15
andc 9-16
andc. 9-16
andi. 9-17
andis. 9-18
architecture, PowerPC 1-3
arithmetic compares 2-11
arithmetic instructions 2-38
asynchronous interrupts 5-1
B
b 9-19
ba 9-19
bc 9-20
bca 9-20
bcctr 9-26
bcctrl 9-26
bcl 9-20
bcla 9-20
bclr 9-30
bclrl 9-30
bctr 9-27
bctrl 9-27
bdnz 9-21
bdnza 9-21
bdnzf 9-21
bdnzfa 9-21
bdnzfl 9-21
bdnzfla 9-21
bdnzflr 9-31
bdnzflrl 9-31
bdnzl 9-21
bdnzla 9-21
bdnzlr 9-31
bdnzlrl 9-31
bdnzt 9-21
bdnzta 9-21
bdnztl 9-21
bdnztla 9-21
bdnztlr 9-31
bdnztlrl 9-31
bdz 9-21
bdza 9-21
bdzf 9-22
bdzfa 9-22
bdzfl 9-22
bdzfla 9-22
bdzflr 9-31
bdzflrl 9-31
bdzl 9-21
bdzla 9-21
bdzlr 9-31
bdzlrl 9-31
bdzt 9-22
bdzta 9-22
bdztl 9-22
bdztla 9-22
bdztlr 9-31
bdztlrl 9-31
beq 9-22
beqa 9-22
beqctr 9-27
beqctrl 9-27
beql 9-22
beqlr 9-31
beqlrl 9-31
bf 9-22