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Cache Operations 4-3
cache line. The remaining address bits (A
22
:27
) serve as an index to the cache array. The two cache
lines that correspond with the same line index are called a congruence class.
Table 4-3 shows the values of
m
and
n
for various cache array sizes.
When the ICU or DCU requests a cache line from main memory (an operation called a cache line fill),
a least-recently-used (LRU) policy determines which cache line way will receive the requested line.
The index, determined by the instruction or data address, selects a congruence class. Within a
congruence class, the most recently accessed line (in either way A or way B) is retained and the LRU
bit in the associated tag array marks the other line as LRU. The LRU line then receives the requested
instruction or data words. After the cache line fill, the LRU bit is set to identify as LRU the line opposite
the line just filled.
4.2 ICU Overview
The ICU manages instruction transfers between external cachable memory and the instruction queue
in the execution unit.
Table 4-2. ICU and DCU Cache Array Organization
Tags (Two-way Set) Cache Lines (Two-way Set)
Way AWay BWay AWay B
A
0:
m
–1
Line 0 A
0:
m
–1
Line 0 Line 0 Line 0
A
0:
m
–1
Line 1 A
0:
m
–1
Line 1 Line 1 Line 1
•
•
•
•
•
•
•
•
•
•
•
•
A
0:
m
–1
Line
n
–2 A
0:
m
–1
Line
n
– 2 Line
n
– 2 Line
n
–2
A
0:
m
–1
Line
n
–1 A
0:
m
–1
Line
n
– 1 Line
n
– 1 Line
n
–1
Table 4-3. Cache Sizes, Tag Fields, and Lines
Instruction Cache Array Data Cache Array
Array Size
m
(Tag Field Bits)
n
(Lines)
m
(Tag Field Bits)
n
(Lines)
0KB————
4KB 22 (0:21) 64 20 (0:19) 64
8KB 22 (0:21) 128 20 (0:19) 128
16KB 22 (0:21) 256 20 (0:19) 256
32KB 22 (0:21) 512 20 (0:19) 512