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A-18 PPC405 Core User’s Manual
lwz RT, D(RA) Load word from EA = (RA|0) + EXTS(D) and place in
RT,
(RT)
← MS(EA,4).
9-91
lwzu RT, D(RA) Load word from EA = (RA|0) + EXTS(D) and place in
RT,
(RT)
← MS(EA,4).
Update the base address,
(RA)
← EA.
9-92
lwzux RT, RA, RB Load word from EA = (RA|0) + (RB) and place in RT,
(RT)
← MS(EA,4).
Update the base address,
(RA)
← EA.
9-93
lwzx RT, RA, RB Load word from EA = (RA|0) + (RB) and place in RT,
(RT)
← MS(EA,4).
9-94
macchw RT, RA, RB prod
0:31
← (RA)
16:31
x (RB)
0:15
signed
temp
0:32
← prod
0:31
+ (RT)
(RT)
← temp
1:32
9-95
macchw. CR[CR0]
macchwo XER[SO, OV]
macchwo. CR[CR0]
XER[SO, OV]
macchws RT, RA, RB prod
0:31
← (RA)
16:31
x (RB)
0:15
signed
temp
0:32
← prod
0:31
+ (RT)
if ((prod
0
= RT
0
) ∧ (RT
0
≠ temp
1
)) then
(RT)
← (RT
0
||
31
(¬RT
0
))
else (RT)
← temp
1:32
9-96
macchws. CR[CR0]
macchwso XER[SO, OV]
macchwso. CR[CR0]
XER[SO, OV]
macchwsu RT, RA, RB prod
0:31
← (RA)
16:31
x (RB)
0:15
unsigned
temp
0:32
← prod
0:31
+ (RT)
(RT)
← (temp
1:32
∨
32
temp
0
)
9-97
macchwsu. CR[CR0]
macchwsuo XER[SO, OV]
macchwsuo. CR[CR0]
XER[SO, OV]
macchwu RT, RA, RB prod
0:31
← (RA)
16:31
x (RB)
0:15
unsigned
temp
0:32
← prod
0:31
+ (RT)
(RT)
← temp
1:32
9-98
macchwu. CR[CR0]
macchwuo XER[SO, OV]
macchwuo. CR[CR0]
XER[SO, OV]
machhw RT, RA, RB prod
0:15
← (RA)
16:31
x (RB)
0:15
signed
temp
0:32
← prod
0:31
+ (RT)
(RT)
← temp
1:32
9-99
machhw. CR[CR0]
machhwo XER[SO, OV]
machhwo. CR[CR0]
XER[SO, OV]
machhws RT, RA, RB prod
0:31
← (RA)
0:15
x (RB)
0:15
signed
temp
0:32
← prod
0:31
+ (RT)
if ((prod
0
= RT
0
) ∧ (RT
0
≠ temp
1
)) then
(RT)
← (RT
0
||
31
(¬RT
0
))
else (RT)
← temp
1:32
9-100
machhws. CR[CR0]
machhwso XER[SO, OV]
machhwso. CR[CR0]
XER[SO, OV]
Table A-1. PPC405 Instruction Syntax Summary (continued)
Mnemonic Operands Function
Other Registers
Changed Page